In the semiconductor industry, the minimum feature sizes of microelectronic devices are approaching the deep sub-micron regime to meet the demand for faster, lower power microprocessors and digital circuits. The downscaling of complimentary metal oxide semiconductor (CMOS) devices imposes scaling constraints on the gate dielectric material. The thickness of the standard SiO2 gate dielectric layer is approaching a level (˜10 angstrom (Å)) at which tunneling currents may significantly impact transistor performance and reliability. To increase device reliability and reduce electron leakage through the gate dielectric layer that electrically separates the gate electrode material from the active region (transistor channel) of the device, semiconductor transistor technology is using high dielectric constant (high-k) gate dielectric materials. Dielectric materials featuring a dielectric constant greater than that of SiO2 (k˜3.9) are commonly referred to as high-k materials. In addition, high-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO2, ZrO2) rather than grown on the surface of the substrate (e.g., SiO2, SiOxNy). High-k materials may incorporate metallic silicates or oxides (e.g., Ta2O5 (k˜26), TiO2 (k˜80), ZrO2 (k˜25), Al2O3 (k˜9), HfSiOx (k˜10-15), HfO2 (k˜25)). High-K materials such as these allow increased physical thickness of the gate dielectric layer to decrease leakage current while maintaining a high capacitance for reducing electrical thickness, thereby increasing performance.
Threshold voltage (Vt) instability and mobility degradation are among the challenges for integration of high-k dielectric materials into gate stacks. In addition, the gate electrode material may chemically react with or diffuse into the underlying gate dielectric material. In one example, a polycrystalline silicon (poly-Si) gate electrode layer may react with a Hf-containing high-k material (e.g., HfO2 or HfSiOx) and form a detrimental silicide material. One proposed solution for these problems includes depositing an additional layer (e.g., a diffusion barrier) between the gate dielectric layer and the gate electrode layer. However, this adds a deposition step to the overall manufacturing process and creates new interfaces between the layers in the gate stack. The additional layer increases the physical thickness of the gate dielectric material which can reduce the overall dielectric constant of the gate stack and thereby affect the transistor performance.